1. Field of the Invention
The present invention relates to the precise alignment of double-sided patterns and, more particularly, to methods of precisely aligning pattern-defining masks on opposite sides of an opaque substrate, such as a silicon wafer, during the processing of integrated circuits thereon.
2. Description of the Prior Art
Properly oriented patterns are often desired on opposite sides of many different types of opaque bodies constituting articles of manufacture. Such articles may range, for example, from complex double-sided printed circuit boards and miniaturized shadow masks, to decorative articles or panels, to mention but a few. Recently, however, exceedingly precise double-sided pattern alignment has become of critical importance in the manufacture of semiconductor devices, including complex integrated circuits of either the so-called medium scale or large scale integration (MSI or LSI) types. While the mask alignment methods of the present invention will be described in connection with their beneficial application in the manufacture of semiconductor devices and circuits, and particularly those utilizing beam leads, it should be fully appreciated that the alignment methods disclosed and claimed herein may have equal utility in the manufacture of diverse articles including those of the types mentioned hereinabove.
With particular reference to complex IC circuits, they typically include from several to hundreds of active and passive elements fabricated on each of a plurality of discrete, sub-dividable chip-areas initially formed on a common silicon wafer. Such wafers generally measure from 1 to 3 inches in diameter. Each IC chip fabricated on such a wafer may typically have cross-sectional dimensions in a range of 5 to 250 mils in width and/or length, and normally in a range of 1.5 to 20 mils in thickness.
With each chip being of such minute dimensions, it is appreciated that the wafer must be sub-divided along very precisely defined grid lines if the resultant individual IC chips are not to be impaired. Complicating the problem of chip separation is the fact that beam leads are often formed as an integral part of the integrated circuits. These leads are employed to effect both electrical and mechanical connections with an associated header or with terminal pads formed on a supporting substrate. As is well known, of course, beam leads extend outwardly from each chip in a cantilevered manner, which results in such leads actually crossing the respectively adjacent chip separation zones, typically formed as a coordinate pattern of intersecting grid lines on the back side of the wafer. Such beam leads are disclosed, for example, in M. P. Lepselter U.S. Pat. No. 3,335,338. Because of the cantilevered nature of the beam leads, it becomes readily apparent that the processed semiconductor wafer cannot be separated along the observable front side chip spacing zones by a conventional scribing process, utilizing either a diamond cutter or a laser, for example, as such an operation would seriously impair, if not actually sever, the end regions of the cantilevered beam leads.
For that reason, it has been required in the manufacture of beam lead semiconductor devices and ICs to form a chip separation grid pattern on the back side of the opaque wafer, normally of silicon. Such a grid pattern must necessarily be precisely oriented with the boundary lines defining each integrated circuit processed on the front side of the wafer. To appreciate the degree of double-sided pattern alignment accuracy required, the maximum allowable tolerance variation between the patterns for very high circuit density wafers is often restricted to a range of one to several microns.
In view of such stringent alignment accuracy, it became readily apparent very early in the development of IC manufacturing processes that the use of mechanically mounted, pre-aligned masks were generally unsuitable because of their inherent mechanical tolerance variations. As a result, infrared light has often been employed heretofore in situations where the substrate thickness is not more than 1.5 to 2 mils in thickness. Even then, however, the resolution of the metal intraconnections and beam leads on the front side of the wafer is normally less than ideal, primarily because of depth-of-field problems. Further, when the adjacent chip separation grid pattern lines are exceedingly close, relatively expensive and complex pattern magnification systems are generally required, involving either expensive microscopes or systems utilizing a CRT for display purposes.
It is appreciated, of course, that whenever infra-red light is employed, the composition of the substrate, as well as the thickness thereof, has a considerable bearing on the effective resolution of an active side metallized circuit pattern observed therethrough. With the advent of silicon wafers having specialized surface coatings formed thereon, such as sapphire or spinel on silicon (employed to attain certain optimized operating characteristics), the use of infrared light may be even further restricted as a means of achieving precise pattern alignment.
The use of infrared light for mask alignment purposes has been completely ruled out in one IC manufacturing process wherein a magnetic layer is formed on the back side of the wafer. Such a layer is often desired to facilitate the handling of the wafers during at least certain integrated circuit processing steps before the later are packaged into discrete circuit modules. Such a magnetic layer effectively blocks infrared light, thus preventing the use of such light for double-sided pattern alignment. For further details with respect to the use of magnetic coatings, reference is made to U.S. Pat. No. 3,692,168, issued Sept. 19, 1972, of H. E. Hughes, J. S. Morton and M. H. Wachs; and U.S. Pat. No. 3,612,955, issued Oct. 12, 1971, of A. D. Butherus, M. C. Huffstutler and J. A. Morton, both of which patents are assigned to the Bell Telephone Laboratories, Inc.
In view of the problems encountered heretofore in readily established precise mask-defined pattern alignment on opposite sides of semiconductors wafers, and particularly when a magnetic coating is present, an alternative technique was developed and is disclosed in U.S. Pat. No. 3,759,767, of D. C. Walls, commonly assigned to the assignee of the present invention. The alignment method disclosed therein involves forming a plurality of alignment holes (preferably with a laser) partially through the wafer at specified alignment sites on the circuit side thereof. Thereafter, a portion of the back side of the wafer is removed to join the holes to the back side. In accordance with a method of making semiconductor devices, a photoresist layer is then formed on the back side of the substrate so that the holes remain distinguishable. The chip separation mask is then positioned on the photoresist layer and aligned with the holes. While this technique can provide accurate double-sided pattern alignment, it necessitates a number of carefully controlled and time consuming process steps.
Attempts have also been made to etch (as distinguished from drill) microscopic alignment holes completely through a silicon wafer. Unfortunately, such an etching process requires additional masking steps, is time consuming, and produces holes of relatively larger diameter than those produced with a laser, for example, because of undesired lateral etching.